In general, semiconductor devices or integrated circuits (ICs) have utilized either trench isolation or selective oxidation such as local oxidation of silicon (LOCOS) to electrically insulate or isolate various portions of the semiconductor device from other portions of the device. Trench isolation typically involves etching a recess or trench in the silicon (Si) substrate, filling the trench with an insulation material such as silicon oxide by using, for example, tetraethylorthosilicate (TEOS), and planarizing the insulation material. LOCOS techniques typically involve growing a pad or liner oxide, depositing a nitride film, patterning and etching the nitride film and then growing or forming an oxide on a Si substrate and heating the substrate so that the exposed portions of the oxide grow to form an insulating medium in the semiconductor device.
The isolation regions for semiconductor devices vary in size depending on parameters or requirements necessary for proper electric isolation and charge carrier isolation in the device. For example, in complementary metal oxide semiconductor (CMOS) devices including integrated circuits (ICs) such as logic and memory components, both wide isolation regions and narrow isolation regions are necessary on the Si substrate to efficiently isolate certain areas of the semiconductor chip or device. Certain areas of the semiconductor chip require large isolation regions while others require small isolation regions due to different voltage requirements, dopant types, increased circuit packing density, dopant concentrations, or other criteria associated with IC design.
As various semiconductor devices or ICs have become smaller, the demands for the efficient use of space by isolation regions has increased. Heretofore, semiconductor devices have utilized either entirely trench isolation techniques, modified LOCOS techniques, or LOCOS techniques to provide isolation for the device. The use of trench isolation regions are advantageous due to their relatively small size. However, trench isolation regions are susceptible to unevenness or dishing when the trench isolation regions of different widths are planarized. Dishing is a particular problem when wide and narrow isolation regions are utilized by the semiconductor device because the insulating material (e.g., TEOS) tends to be removed from the wide isolation regions more quickly than from the narrow isolation regions. Conventional LOCOS techniques can be disadvantageous because they require relatively larger lateral spacing on the semiconductor substrate.
Thus, there is a need for wide and narrow isolation regions on a semiconductor structure which are less susceptible to dishing problems. There is also a need for a method of fabricating a semiconductor device having isolation regions formed by a space efficient process which is not susceptible to dishing problems.